The present invention generally relates to a method for coating a thick spin-on-glass (SOG) layer on a semiconductor structure and more particularly, relates to a method for coating a thick SOG layer on a semiconductor structure without cracking problems by adding a stress buffer layer of silicon oxide in-between two spin-on-glass layers on top of the semiconductor structure.
Spin-on-glass (SOG) is frequently used for gap fill and planarization of inter-level dielectrics (ILD) in multi-level metalization structures. It is a desirable material for use in low-cost fabrication of IC circuits. Most commonly used SOG materials are of two basic types; an inorganic type of silicate based SOG and an organic type of siloxane based SOG. One of the commonly used organic type SOG materials is a silicon oxide based polysiloxane which is featured with radical groups replacing or attaching to oxygen atoms. Based on these two basic structures, the molecular weight, the viscosity and the desirable film properties of SOG can be modified and adjusted to suit the requirement of specific IC fabrication process.
SOG film is typically applied to a pre-deposited oxide surface as a liquid to fill gaps and steps on the substrate. Similar to the application method for photoresist films, a SOG material can be dispensed onto a wafer and spun with a rotational speed which determines the thickness of the SOG layer desired. After the film is evenly applied to the surface of the substrate, it is cured at a temperature of approximately 400xc2x0 C. and then etched back to obtain a smooth surface in preparation for a capping oxide layer on which a second interlevel metal may be patterned. The purpose of the etch-back step is to leave SOG between metal lines but not on top of the metal, while the capping oxide layer is used to seal and protect SOG during further fabrication processes. The siloxane based SOG material is capable of filling 0.15 micron gaps and therefore it can be suitably used in 0.25 micron technology.
When fully cured, silicate SOG has similar properties like those of silicon dioxide. Silicate SOG does not absorb water in significant quantity and is thermally stable. However, one disadvantage of silicate SOG is the large volume shrinkage during curing. As a result, the silicate SOG retains high stress and cracks easily during curing and further handling. The cracking of the SOG layer can cause a serious contamination problem for the fabrication process. The problem can sometimes be avoided by the application of only a thin layer, i.e. 1000xcx9c2000 xc3x85 of the silicate SOG material.
In order to reach a final thickness of several thousand angstrom of the SOG layer, several thinner layers of the silicate SOG material must be deposited. However, it has been found that even by depositing multiple thinner layers of SOG, i.e. in as many as four separate deposition steps, the final SOG layer obtained may still have a cracking problem during curing or subsequent processing. The problem becomes even more severe when structures of high aspect ratio or poor topography are involved. The conventional multi-step deposition technique for depositing a thick SOG layer leads to either a cracking problem or poor planarization.
It is therefore an object of the present invention to provide a method for coating a thick spin-on-glass layer without the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for coating a thick spin-on-glass layer on a semiconductor structure without cracking problems.
It is a further object of the present invention to provide a method for coating a thick spin-on-glass layer on a semiconductor structure that has improved planarity.
It is another further object of the present invention to. provide a method for coating a thick spin-on-glass layer on a semiconductor structure without cracking problems by incorporating a center stress buffer layer in-between two SOG layers.
It is still another object of the present invention to provide a method for coating a thick spin-on-glass layer on a semiconductor structure without cracking problems by incorporating a PE oxide layer in-between two SOG layers.
In accordance with the present invention, a method for coating a thick spin-on-glass layer on a semiconductor structure without cracking problems is disclosed.
In a preferred embodiment, a method for coating a thick spin-on-glass layer on a semiconductor structure without cracking problems can be carried out by the operating steps of providing a pre-processed semiconductor structure that has a plurality of metal lines formed on top; depositing conformally a first layer of silicon oxide insulating the metal lines; coating a first layer of SOG on top of the first layer of silicon oxide to a thickness of at least 1000 xc3x85; coating a second layer of SOG on top of the first SOG layer to a thickness of at least 1000 xc3x85; annealing the semiconductor structure at a temperature of at least 300xc2x0 C.; depositing a second layer of silicon oxide on top of the second SOG layer to a thickness of at least 1000 xc3x85; coating a third layer of SOG on top of the second layer of silicon oxide to a thickness of at least 1000 xc3x85; coating a fourth layer of SOG on top of the third SOG layer to a thickness of at least 1000 xc3x85; and etching back the third and fourth layers of SOG to substantially planarize the semiconductor structure.
The method for coating a thick spin-on-glass layer on a semiconductor structure without cracking problems may further include the step of depositing a third layer of silicon oxide on top of the fourth layer of SOG to substantially planarize the semiconductor structure, or the step of depositing the first and second layers of silicon oxide by a plasma enhanced oxide deposition technique, or the step of coating the first and second layers of SOG to a total thickness of at least 3000 xc3x85, or the step of coating the third and fourth layers of SOG to a total thickness of at least 3000 xc3x85. The method may further include the step of conducting the annealing process at a first temperature and then at a second temperature that is higher than the first temperature, or the step of conducting the annealing process first at a temperature between about 300xc2x0 C. and about 400xc2x0 C. and then at a temperature between about 350xc2x0 C. and about 450xc2x0 C. The method may further include the step of depositing the second layer of silicon oxide to a thickness of at least 2000 xc3x85, or the step of etching back the third and fourth layers of SOG by a reactive ion etching technique, or the step of depositing the second layer of silicon oxide as a stress buffer layer.
The present invention is further directed to a method for coating a spin-on-glass layer on a semiconductor structure without cracking problems which can be carried out by the steps of first providing a pre-processed semiconductor structure with a plurality of metal lines formed on top; depositing conformally a first layer of silicon oxide insulating the plurality of metal lines; coating a first layer of SOG on top of the first layer of silicon oxide to a thickness of at least 2500 xc3x85; annealing the semiconductor structure at a temperature of at least 300xc2x0 C.; depositing a stress buffer layer of an insulating material on top of the first SOG layer to a thickness of at least 1000 xc3x85; coating a second layer of SOG on top of the stress buffer layer of insulating material to a thickness of at least 2500 xc3x85; and etching back the second layer of SOG to substantially planarize the semiconductor structure.
The method for coating a thick spin-on-glass layer on a semiconductor structure without cracking problems may further include the step of depositing a third layer of silicon oxide on top of the second layer of SOG to substantially planarize the semiconductor structure. The method may further include the step of depositing the first and second layers of silicon oxide by a plasma enhanced oxide deposition technique. The method may further include the step of depositing the stress buffer layer of plasma enhanced oxide. The method may further include the step of conducting the annealing process at a first temperature between about 300xc2x0 C. and about 400xc2x0 C. and then at a second temperature between about 350xc2x0 C. and about 450xc2x0 C. The method may further include the step of depositing the stress buffer layer of insulating material to a thickness of at least 2000 xc3x85, or the step of etching back the second layer of SOG by a reactive ion etching techique. The method may further include the step of depositing the stress buffer layer with silicon nitride or silicon oxynitride.